Usually, a sample-and-hold circuit is arranged in the input section of an A/D converter or another converting device. It samples the input voltage with prescribed timing, and then holds the sampled voltage until the end of the conversion operation by the converting device set in the next stage. Of the sample-and-hold circuits of this type, a sample-and-hold circuit having 2 inputs and 1 output is represented by number 102 in FIG. 3.
Said sample-and-hold circuit 102 is mainly made of a differential section and an output section. The differential section consists of constant-current source 141 made up of a p-channel MOSFET, 2 systems of differential blocks 151 and 161 having 2 sampling voltages V.sub.in1 and V.sub.in2 input to them, respectively, and current mirror 143 made up of n-channel MOSFETs 144, 145.
The output section consists of constant-current source 142 made up of a p-channel MOSFET and output transistor 147 made up of an n-channel MOSFET.
Said 2 systems of differential blocks 151 (first system) and 161 (second system) have switches 152, 162 and differential circuits 153, 163 made of p-channel MOSFETS. Said differential circuits 153 and 163 are connected to the same constant-current source 141 through switches 152 and 162.
Signal XSEL.sub.1 and signal XSEL.sub.2, which have opposite logic levels, are input to the gate terminals of switches 152 and 162. Only one of these switches is on. Consequently, when current is fed to one of the differential circuits, the current is not fed to the other differential circuit.
Said differential circuit 153 of the first system is made of p-channel MOSFETs 154 and 155 with a common source terminal. Said differential circuit 163 of the second system is made of p-channel MOSFETs 164 and 165 with a common source terminal. One end of hold capacitor C.sub.H1 of differential block 151 and one end of hold capacitor C.sub.H2 of differential block 161 are connected to the gate terminals of p-channel MOSFETs 154 and 164, respectively.
Said differential circuits 153 and 163 of the first and second systems have a constitution such that current mirror 143 is the shared load and they drive the same output transistor 147. The output terminal of output transistor 147 is connected to the gate terminals of p-channel MOSFETs 155 and 165, each of which is one p-channel MOSFET of differential circuits 153 and 163, respectively. One end of each of the hold capacitors C.sub.H1 and C.sub.H2 of the first and second systems is connected to the gate terminals of each of p-channel MOSFETs 154 and 164.
Switches SW.sub.1 and SW.sub.2 are set at one end of each of hold capacitors C.sub.H1 and C.sub.H2 and the connection middle points of the gate terminals of p-channel MOSFETs 154 and 164. When switches SW.sub.1 and SW.sub.2 are on, charging/discharging takes place for hold capacitors C.sub.H1 and C.sub.H2 at voltages V.sub.in1 and V.sub.in2 for sampling.
Now suppose switch SW.sub.1 on the side of differential block 151 of the first system is on, and switch 152 in differential block 151 is off, switch SW.sub.2 on the side of differential block 161 of the second system is off, and switch 162 in differential block 161 is on. In this case, on hold capacitor C.sub.H1 of the first system, sampling voltage V.sub.in1 applied through switch SW.sub.1 appears as the hold voltage (sampling operation), and since switch SW.sub.2 is off, sampling voltage voltage sic! V.sub.in2 is not applied to hold capacitor C.sub.H2 of the second system (hold operation).
From this state, switch 162 is off, the operation of differential block 161 of the second system stops; then, SW.sub.1 is off, hold capacitor C.sub.H1 of the first system is opened from sampling voltage V.sub.in1. Then, switch 152 is on, current is fed to differential block 151 of the first system, and the operation of differential circuit 153 in differential block 151 of the first system is started.
Said sample-and-hold circuit 102 is configured as a voltage follower, which outputs the voltage of the hold capacitor in the differential block from the voltages of hold capacitors C.sub.H1 and C.sub.H2. Now, as switch 152 of the first system is on, differential circuit 153 of the first system operates. Consequently, hold voltage V.sub.CH1 of the first system appears, through output transistor 147, as output voltage V.sub.out.
On the other hand, switch 162 of the second system is off, and differential circuit 163 of the second system stops. In this case, switch SW.sub.2 of the second system is on, sampling voltage V.sub.in2 is applied to hold capacitor C.sub.H2, and charging/discharging occurs at this voltage.
This state is maintained until the end of the conversion operation of the converter set as the next stage after sample-and-hold circuit 102 to the level of hold voltage V.sub.CH1 of the first system. Then, switch 152 of the first system is off, and the operation of differential circuit of the first system stops. Then, switch SW.sub.2 of the second system is off, and hold capacitor C.sub.H2 is opened from sampling voltage V.sub.in2. Then, switch 162 is on, and operation of differential circuit 163 of the second system starts.
As switch 162 is on, operation of p-channel MOSFET 164 connected to hold capacitor C.sub.H2 of the second system starts. As shown in FIG. 4(a), said p-channel MOSFET 164 has the following constitution: impurities are diffused into a p-type silicon substrate; an n-region (n well) is back gate B; and 2 p.sup.+ layers diffused in said back gate B (n well) act as source region S and drain region D. Also, gate electrode G is formed by means of polysilicon film set via a gate oxide film.
In this way, from the constitution shown in FIG. 4(a), in the conventional MOSFET, parasitic capacitors C.sub.GB, C.sub.GS, and C.sub.GD are formed between gate electrode G and back gate B, between gate electrode G and source region S, and between gate electrode and drain region D, respectively. In said p-channel MOSFET 164, these parasitic capacitors C.sub.GB, C.sub.GS, and C.sub.GD are connected in the state shown in FIG. 4(b).
One end of each of said parasitic capacitors C.sub.GS, C.sub.GD, and C.sub.GB and hold capacitor C.sub.H2 is connected to gate electrode G (gate terminal). Differential block 161 of the second system stops, and p-channel MOSFET 164 is off. In this state, V.sub.OUT, a voltage identical to hold voltage V.sub.CH1 of differential block 151 of the first system, is applied to the gate terminal of p-channel MOSFET 165. Consequently, the potential on the side of the source terminal of parasitic capacitors C.sub.GS and C.sub.GB becomes V.sub.CH1 +V.sub.th (where V.sub.th represents the threshold voltage of p-channel MOSFET 165).
Also, since the drain terminal of p-channel MOSFET 164 is connected to the drain terminal of p-channel MOSFET 154, when differential block 151 of the first system operates, the voltage at the drain terminal of p-channel MOSFET 164 becomes potential V.sub.X1 of the gate terminal when output transistor 147 outputs hold voltage V.sub.CH1 of the first system. Consequently, the potential on the side of drain of parasitic capacitor C.sub.GD is V.sub.X1.
In this case, the dependence in potential of various parasitic capacitors C.sub.GS, C.sub.GD, and C.sub.GB on hold capacitor C.sub.H2 is illustrated in FIG. 4(c).
After switch SW.sub.2 is off from this state, switch 162 becomes on, and differential circuit 161 of the second system makes transition from the sampling state to the holding state, the supply of current to differential circuit 163 of the second system starts, and the potential of one end of each of the parasitic capacitors C.sub.GS and C.sub.GB rises from V.sub.CH1 +V.sub.th to the potential of the drain terminal of constant-current source 141. Also, the potential at one end of parasitic capacitor C.sub.GD changes from said potential V.sub.X1 to potential V.sub.X2 of the gate terminal when output transistor 147 outputs hold voltage V.sub.CH2 of the second system.
In this way, when the transition from the sampling state to the holding state occurs, the terminal potential of p-channel MOSFET 164 connected to hold capacitor C.sub.H2 varies. Consequently, current for charging/discharging of parasitic capacitors C.sub.GS, C.sub.GD, and C.sub.GB flows through hold capacitor C.sub.H2, the voltage of hold capacitor C.sub.H2 after transition to the holding state becomes different than the voltage of hold capacitor C.sub.H2 in the sampling state, and error in the detected voltage takes place.
Among said parasitic capacitors C.sub.GS, C.sub.GD, and C.sub.GB, for parasitic capacitor C.sub.GB between the gate and back gate, when power source voltage V.sub.ee is applied to back gate B, there is no variation in the sampling state and the holding state. Consequently, it is possible to eliminate its influence.
However, the voltage at the source terminal and drain terminal of the MOSFET connected to the hold capacitor on the side in the sampling state is influenced by the value of output voltage V.sub.out output by the other system in the holding state. Consequently, it is impossible to get rid of the influence of parasitic capacitors C.sub.GS, C.sub.GD. There is a demand to solve this problem.
The purpose of the present invention is to solve the aforementioned problems of the conventional methods by providing a type of sample-and-hold circuit free of the influence of parasitic capacitance.